The engineering evidence behind ACIX.

Engineering record

Independent work and professional experience.

Detailed case studies below cover independent work only. Previous employment and consultancy are represented at capability level; confidential client or employer architectures, interfaces, implementation details and technical results are not reproduced here.

1. 01

   Professional FPGA and embedded-systems experience

   Experience gained across internship, consultancy and employment roles. Confidential project details are not reproduced.

   Professional engineering work has included FPGA and RTL development, embedded systems, data-acquisition and control platforms, hardware–software integration, signal processing, system optimisation, analogue electronics and engineering verification.

   Digital systems

   FPGA and RTL design, heterogeneous SoC development, embedded Linux, microcontroller firmware, hardware interfaces, debugging and verification.

   Hardware and integration

   Analogue electronics, instrumentation, PCB bring-up, system integration, laboratory validation and engineering documentation.

2. 02

   Signal-processing pipeline

   Independent research.

   Independent research into an FMCW LiDAR acquisition and processing chain, taken as far as a working signal path in fabric and verified against a reference model.

   Acquisition and processing

   An acquisition chain of ADC capture → NCO → mixer → FIR decimation ×32 → FFT, with PetaLinux bring-up and Python tooling, and on-chip debug via ILA and Tcl automation.

   Verification

   Fixed-point conversion checked bit-accurately against a MATLAB reference model across roughly 1,000 Monte Carlo runs with zero divergence, alongside corner-case and reset testing.

   ~1,000 runs Monte Carlo verification, zero divergence
3. 03

   Signal generator, Cyclone V SoC

   Independent project.

   A signal generator built on an Altera Cyclone V SoC with an ARM Cortex-A9 hard processor system: a purpose-built analogue front end, a parallel signalling interface implemented in both analogue hardware and FPGA fabric for processing, and signal generation driven from Linux running on the ARM core.

Published research

MEng thesis, Imperial College London.

Completed 2026. Power hardware-in-the-loop interfaces — specifically DAC/ADC delay compensation and H∞ synthesis for stabilising active inverter systems. Published by Imperial College London under a Creative Commons licence.

Demonstrated competences

What the engineering record evidences.

Professional capabilities are stated here as general skills and tool experience, rather than as descriptions of confidential client or employer projects.

• FPGA / RTL

  VHDL, Verilog and SystemVerilog; RTL architecture; FSMs; control/datapath separation; pipelining; fixed-point arithmetic; parameterised, streaming architectures; hardware–software partitioning.

• Platforms and toolflow

  AMD/Xilinx Zynq-7000, Zynq UltraScale+, ZCU104 and Artix-7; Intel/Altera Cyclone V on an independent project; Vivado, Vitis and PetaLinux; ModelSim/QuestaSim; synthesis, place-and-route, static timing analysis and timing closure.

• Interfaces and clocking

  AXI4, AXI4-Stream, AXI-Lite and AXI DMA; SPI, UART, I²C and Ethernet integration; clock-domain crossing and reset-domain design; metastability-aware, multi-clock systems.

• Embedded software

  Embedded Linux and PetaLinux build/deploy; bare-metal firmware; STM32 and other microcontroller development; Python hardware-control tooling.

• Analogue and instrumentation

  Analogue front-end design; low-noise amplification; active and passive filtering; mains-rejection design; LTspice/SPICE modelling; grounding, shielding and signal integrity.

• PCB and lab

  Schematic capture and PCB design in KiCad, with Altium exposure; PCBA bring-up and SMD rework; oscilloscopes, logic analysers, spectrum and network analysers, function generators and bench supplies.

• Languages and tooling

  Python, C, C++, MATLAB, Simulink, Tcl and Bash; Git, GitHub and GitHub Actions; PyTest.

  Exposure only: C++ depth, ROS2, RTOS, formal verification